Posts by Collection

Compute-in-memory architecture and chip design

Constructing architecture, chips and computing systems that integrate storage and computation together using emerging post-Moore devices such as memristors, targeting artificial intelligence and communication algorithms.

Pipelined dataflow architecture and chip design

Constructing efficient chips and hardware systems for AI and signal processing using architectural techniques such as multi-stage pipelining, out-of-order execution, heterogeneous on-chip networks, and AI-assisted design.

AI-aided chip architecture design

Exploiting artificial intelligence for chip architecture design and optimization.

LDPC post-processor architecture and method for low error floor conditions

US Patent 9,793,923, 2017

Authors: Yaoyu Tao, Joyce Kwong
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Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes

IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 66, Issue 10, 2019

Authors: Yaoyu Tao, Shuanghong Sun, Zhengya Zhang
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A 3.25 Gb/s, 13.2 pJ/b, 0.64 mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS

2019 IEEE Symposium on VLSI Circuits (VLSI), 2019

Authors: Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang
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A configurable successive-cancellation list polar decoder using split-tree architecture

IEEE Journal of Solid-State Circuits, Volume 56, Issue 2, 2021

Authors: Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang
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HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer

54th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021

Authors: Yaoyu Tao, Zhengya Zhang
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DNC-Aided SCL-Flip Decoding of Polar Codes

2021 IEEE Global Communications Conference (GLOBECOM), 2021

Authors: Yaoyu Tao, Zhengya Zhang
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Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search

2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), 2023

Authors: Lei Cai, Jing Wang, Lianfeng Yu, Bonan Yan, Yaoyu Tao*, Yuchao Yang*
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eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs

2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023

Authors: Junkang Zhu*, Yaoyu Tao*, Zhengya Zhang
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一种面向存算一体系统的有限域纠错编解码方法及系统

CN202311037278.1, 2023

Authors: 陶耀宇; 史代璟; 杨玉超; 燕博南

VO2 memristor-based frequency converter with in-situ synthesize and mix for wireless internet-of-things

Nature Communications volume 15, Article number: 1523, 2024

Authors: Chang Liu, Pek Jun Tiw, Teng Zhang, Yanghao Wang, Lei Cai, Rui Yuan, Zelun Pan, Wenshuo Yue, Yaoyu Tao*, Yuchao Yang*
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一种可编程多时间尺度储备池计算单元及其操作方法

CN2024107436937, 2024

Authors: 杨玉超；杨振；张腾；陶耀宇；黄如

基于电化学随机存取存储器的全并行向量外积计算操作方法

CN2024107436922, 2024

Authors: 杨玉超；杨振；路英明；陶耀宇；张腾；黄如

一种基于电化学掺杂的可调LIF神经元硬件单元

CN2024108200368, 2024

Authors: 杨玉超；杨振；张腾；陶耀宇；黄如

一种面向忆阻型器件的基于有限状态机的写入验证方案

CN2024108261130, 2024

Authors: 杨玉超；余连风；陶耀宇；杨宇翔

A scalable universal Ising machine based on interaction-centric storage and compute-in-memory

Nature Electronics volume 7, Pages 904–913, 2024

Authors: Wenshuo Yue, Teng Zhang, Zhaokun Jing, Kai Wu, Yuxiang Yang, Zhen Yang, Yongqin Wu, Weihai Bu, Kai Zheng, Jin Kang, Yibo Lin, Yaoyu Tao, Bonan Yan*, Ru Huang, Yuchao Yang*
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一种基于忆阻器存内计算架构的卷积神经网络权重映射及像素级推理仿真方案

CN2024112760540, 2024

Authors: 杨玉超；李志远；陶耀宇；朱奕航；蔡磊

Full van der Waals Ambipolar Ferroelectric Configurable Optical Hetero‐Synapses for In‐Sensor Computing

Advanced Materials, 2401060, 2024

Authors: Jinxuan Bai, Dawei He, Bingjie Dang, Keqin Liu, Zhen Yang, Jiarong Wang, Xiaoxian Zhang*, Yongsheng Wang*, Yaoyu Tao*, Yuchao Yang*
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MeMCISA: Memristor-Enabled Memory-Centric Instruction-Set Architecture for Database Workloads

2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2024

Authors: Yihang Zhu, Lei Cai, Lianfeng Yu, Anjunyi Fan, Longhao Yan, Zhaokun Jing, Bonan Yan, Pek Jun Tiw, Yuqi Li, Yaoyu Tao*, Yuchao Yang*
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一种全模拟数据流的神经常微分方程求解器及其计算方法

CN202411573862.3, 2024

Authors: 杨玉超；孙玉丽；陶耀宇；余连风

一种基于忆阻器存内计算架构的衣物模拟加速方案

CN2024115995707, 2024

Authors: 杨玉超；龙洁；陶耀宇；余连风

Physical unclonable in-memory computing for simultaneous protecting private data and deep learning models

Nature Communications volume 16, Article number: 1031, 2025

Authors: Wenshuo Yue, Kai Wu, Zhiyuan Li, Juchen Zhou, Zeyu Wang, Teng Zhang, Yuxiang Yang, Lintao Ye, Yongqin Wu, Weihai Bu, Shaozhi Wang, Xiaodong He, Xiaobing Yan*, Yaoyu Tao, Bonan Yan*, Ru Huang & Yuchao Yang*
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Energy‐Efficient Online Training with In Situ Parallel Computing on Electrochemical Memory Arrays

Advanced Intelligent Systems, 2401068, 2025

Authors: Yingming Lu, Zhen Yang, Yaoyu Tao, Lei Cai, Teng Zhang, Longhao Yan, Ru Huang, Yuchao Yang*
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Non-Binary LDPC Arithmetic Error Correction For Processing-in-Memory

Under review at TCAS-I, 2025

Authors: Daijing Shi, Yihang Zhu, Anjunyi Fan, Yaoyu Tao*, Yuchao Yang*, Bonan Yan*
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Fast and reconfigurable sort-in-memory system enabled by memristors

Accepted by Nature Electronics, 2025

Authors: Lianfeng Yu, Teng Zhang, Zeyu Wang, Xile Wang, Zelun Pan, Bowen Wang, Zhaokun Jing, Jiaxin Liu, Yuqi Li, Yihang Zhu, Bonan Yan, Yaoyu Tao*, Yuchao Yang*
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Talk 1 on Relevant Topic in Your Field

发布时间： March 01, 2012

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Tutorial 1 on Relevant Topic in Your Field

发布时间： March 01, 2013

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Talk 2 on Relevant Topic in Your Field

发布时间： February 01, 2014

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Conference Proceeding talk 3 on Relevant Topic in Your Field

发布时间： March 01, 2014

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Hardware Architecture for Intelligent Computing Systems

Principal instructor, Bachelor's level course, fall semester, Yuanpei College, Peking University, 2024

Course website

Hardware Fundamentals for Artificial Intelligence: From Physical Devices to Chip Architecture

Principal instructor, Bachelor's level course, spring semester, Yuanpei College, Peking University, 2025

Course website