A 3.25 Gb/s, 13.2 pJ/b, 0.64 mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS
2019 IEEE Symposium on VLSI Circuits (VLSI), 2019
A 0.64mm2 configurable successive-cancellation list polar decoder is designed in 40nm CMOS for 5G wireless applications. The decoding tree is split to 4 subtrees to be decoded by 4 sub-decoders in parallel to improve throughput and cut latency by 4×. To maximize utilization, 8 frames are interleaved and decoded simultaneously to increase throughput by another 8× to 3.25Gb/s for code length up to 1024b. Dynamic clock gating reduces the peak power dissipation to 42.8mW at 0.9V, or 13.2pJ/b.
Authors: Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang
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