One paper accepted at Nature Electronics
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One paper, featuring fast and reconfigurable sort-in-memory system enabled by memristors, is accepted by Nature Eletronics.
2025
One paper accepted at Nature Communications
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One paper, featuring memristor-enabled fully on-chip physical unclonable function named as RePACK , is accepted by Nature Communications.
One paper accepted at HPCA 2025
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One paper, featuring Programmable Probabilistic Processing Unit Architecture with Accept/Reject Prediction & Multicore Pipelining for Causal named PROCA, is accepted by 2025 IEEE International Symposium on High-Performance Computer Architecture (HPCA).
2024
One paper accepted at IEDM 2024
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One paper, featuring PCM memristor based neural manifold learning accelerator with conductance drift compensation, is accepted by IEDM 2024 as regular paper.
学术报告：后摩尔器件多域融合的芯片架构与电路
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北京航空航天大学集成电路学院学术报告：后摩尔器件多域融合的芯片架构与电路
受邀报告：基于后摩尔器件的多计算域融合芯片架构与电路
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第26届中国电子学会青年年会暨第五届半导体青年学术会议受邀报告：基于后摩尔器件的多计算域融合芯片架构与电路。
One paper accepted at Advanced Materials
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One paper, featuring full van der waals ambipolar ferroelectric configurable optical hetero‐synapses for in‐sensor computing, is accepted by Advanced Materials.
受邀报告：基于后摩尔器件的存算一体芯片架构与电路
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中国科学院上海微系统研究所受邀报告：基于后摩尔器件的存算一体芯片架构与电路。
One paper accepted at Nature Electronics
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One paper, featuring A scalable universal Ising machine based on interaction-centric storage and compute-in-memory, is accepted by Nature Electronics.
One paper accepted at MICRO 2024
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One paper, featuring memristor-enabled memory-centric instruction-set architecture (MeMCISA) aiming to efficiently accelerate versatile workloads in modern database systems, is accepted by MICRO 2024 as regular paper.
学术报告：SOI年度学术交流会
发布时间：
SOI年度学术交流会报告：基于后摩尔器件的多计算域融合芯片架构与电路。
学术报告：半导体芯片技术的演进与前沿趋势
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北京大学信息工程学院学术报告：半导体芯片技术的演进与前沿趋势路。
项目汇报：南澳科学会议-物态调控学术研讨会暨项目联合启动会
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受邀参加南澳科学会议作项目汇报：基于莫尔超晶格光子学原型器件构建
圆桌对话：中关村论坛-侨海创新发展论坛
发布时间：
受邀参加中关村论坛-侨海创新发展论坛圆桌对话环节，主题为：智能未来 - 探索人工智能的无限潜能
One paper accepted at Nature Communications
发布时间：
One paper, featuring VO2 memristor-based frequency converter with in-situ synthesize and mix for wireless internet-of-things, is accepted by Nature Communications.
2023
One paper accepted at IEEE Journal of Solid-State Circuits (JSSC)
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One paper, featuring A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration, is accepted by IEEE Journal of Solid-State Circuits (JSSC).
One paper accepted at HPCA 2023
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One paper, featuring an Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEsnamed as eNODE, is accepted by 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA).
One paper accepted at FPGA 2023
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One paper, Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search, is accepted by 2023 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA).
2022
Two papers accepted at ISCAS 2022
发布时间：
Two papers, Fast and scalable memristive in-memory sorting with column-skipping algorithm, and High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder, are accepted by 2022 IEEE International Symposium on Circuits and Systems (ISCAS).
2021
One paper accepted at GLOBECOM 2021
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One paper, DNC-aided SCL-flip decoding of polar codes, are accepted by 2021 IEEE Global Communications Conference (GLOBECOM). The paper won Best Paper Award.
One paper accepted at MICRO 2021
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One paper, HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer, is accepted by 54th IEEE/ACM International Symposium on Microarchitecture (MICRO).
One paper accepted at IEEE Journal of Solid-State Circuits (JSSC)
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One paper, A configurable successive-cancellation list polar decoder using split-tree architecture, is accepted by IEEE Journal of Solid-State Circuits (JSSC).
2019
One paper accepted at IEEE Symposium on VLSI Circuits (VLSI)
发布时间：
One paper, A 3.25 Gb/s, 13.2 pJ/b, 0.64 mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS, is accepted by 2019 IEEE Symposium on VLSI Circuits (VLSI) .
One paper accepted at IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
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One paper, Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes, is accepted by IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I).