One paper accepted at IEEE Symposium on VLSI Circuits (VLSI)

One paper, A 3.25 Gb/s, 13.2 pJ/b, 0.64 mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS, is accepted by 2019 IEEE Symposium on VLSI Circuits (VLSI) .