Pipelined dataflow architecture and chip design

Dr. Yaoyu Tao research projects include 4G low-density parity-check (LDPC) code chips, 5G polar code (Polar code) chips, and other dataflow architecture chips. Through collaborations with companies such as Qualcomm and Texas Instruments, successful industrialization was achieved. Based on earlier research, and looking ahead to the demands of future 6G intelligent communication, the exploration of AI-assisted encoding/decoding architectures was conducted (including the world-first proposal to use differential neural computers for polar code error correction). Additionally, a high-energy-efficiency frequency generation architecture based on the post-Moore memristor device was developed (world-first proposal to use volatile vanadium oxide devices for in-situ frequency generation and hybrid architecture). Relevant work have been published in high-impact international journals and conferences such as Nature Communications, JSSC, TCAS-I, ISSCC, Globecom, and VLSI, among other. In addition, the research in this field has led to several Chinese and U.S. invention patents, some of which were successfully transferred to Texas Instruments (with evidence of over 150 million chips shipped) and Qualcomm, achieving mass production and shipping. These patents have been cited in commercial technology patents by several top chip companies, including Qualcomm, Huawei, and Texas Instruments.

设计了多款4G低密度奇偶校验码（LDPC码）芯片、5G极化码（Polar码）芯片等数据流架构芯片，性能指标达到当时国际领先水平，并通过与高通、德州仪器等公司的合作成功实现产业化。在前期研究基础上，面向未来6G智能化通信的需求，探索了人工智能辅助编解码架构（国际上率先提出利用微分神经计算机进行极化码纠错）、基于后摩尔新型忆阻器件的高能效频率生成与混合芯片架构（国际上率先提出利用易失性氧化钒器件实现原位频率生成与混合）。相关工作发表Nature Communications、集成电路最高期刊JSSC、电路系统顶级期刊TCAS、全球“芯片奥林匹克”会议ISSCC、通信最高会议IEEE Global Communication Conference、芯片体系架构顶尖会议VLSI等十余篇国际高水平期刊与会议论文。此外，在该领域的工作已产生多项中国、美国发明专利，部分专利成功转移至德州仪器（开具证明累计出货芯片超1.5亿颗）、高通等公司实现量产出货，并被多家顶尖芯片公司（包括高通、华为、德州仪器等）在其商用技术专利中引用。